Hachinohe Institute of Technology · Faculty of Engineering · 教授

Research keywords微小演算遅れ時間・Dynamic Reconfigration・Parallel VLSI Processor・Small Delay Time・並列VLSIプロセッサ・動的再構成・遠隔操作ロボット

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• VLSI architecture based on packet data transfer scheme and its application
• Multi-Layer Printed Wiring Board with Built-In Soldering Heater and 3D Implementation of Dynamically Reconfigurable Highly Parallel Processors
• ビットシリアルアーキテクチャに基づくロボット制御用再成可能VLSIプロセッサの構成
• Functional-Unit-Level Packet Data Transfer Scheme for A Highly Parallel VLSI Processor

• 多入力算術演算器の動的再構成に基づく3次元画像計測用3次元機能メモリの構成
• 再構成可能並列VLSIプロセッサと知能ロボット制御への応用に関する研究
• Study on Multi layer Printed Wiring Board with Built-In Soldering Heater and Its Application for 3D structured Highly Parallel Processors
• 動的再構成に基づく知能ロボット用並列VLSIプロセッサの最適設計

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