Hiroshima Institute of Technology · Graduate School of Engineering

Research keywordsformal verification・SAT solving・SMT scheduling・PCB inspection routing・requirements analysis・monitor synthesis

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• 授業におけるPC操作情報を用いた活動状況可視化手法 , 教育システム情報学会誌, 36( 2), 107- 117, 2019年01月07日,2019
• Modeling and Solving Open Shop Cooperative Task Scheduling Problems Based on Satisfiability Modulo Theories , Scientiae Mathematicae Japonicae, 81( 2), 183- 193, 2018年01月, https://doi.org/10.32219/isms.81.2_1832018
• Coverage-Driven Design Verification Using a Diverse SAT Solver , IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, E100-A( 7), 1481- 1487, 2017年07月01日, https://doi.org/10.1587/transfun.E100.A.14812017
• 形式手法を用いたSysMLシステム要求仕様に対する制約解析 , 電気学会論文誌C, 137( 6), 809- 814, 2017年06月01日, https://doi.org/10.1541/ieejeiss.137.8092017

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