Kumamoto University · Institute for Semiconductor and Digital Research and Education · 准教授

Research keywords接合・シリコン貫通電極・ウエハ研削・バンプ・半導体・3次元集積回路・3次元実装・半導体デバイス

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• In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging2022 · IEEE Transactions on Components, Packaging and Manufacturing Technology
• Analysis and evaluation of noise coupling between through-silicon-vias2021 · IEICE Electronics Express
• 3-D CMOS Chip Stacking for Security ICs Featuring Backside Buried Metal Power Delivery Networks With Distributed Capacitance2021 · IEEE Transactions on Electron Devices
• Fully epitaxial giant magnetoresistive devices with half-metallic Heusler alloy fabricated on poly-crystalline electrode using three-dimensional integration technology2020 · Acta Materialia

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