Tohoku University · Graduate School of Information Science · 教授

Research keywordsstereo matching・VLSI processors・robot vision hardware・FPGA acceleration・block matching・vehicle detection・obstacle avoidance・embedded vision

This is a public-data preview. Personalized fit, contact angles, and saved workflows require sign-in.

• Genetic approach to minimizing energy consumption of VLSI processors using multiple supply voltagesM Hariyama, T Aoyama, M Kameyama
• An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid ArchitectureShota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
• Data-Transfer-Bottleneck-Less Architecture for FPGA-Based Quantum Annealing SimulationChia-Yin Liu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama
• An SIMD Architecture for Shortest-Path Search and Its FPGA ImplementationYasuhiro Takei, Masanori Hariyama, Michitaka Kameyama

• 高安全知能集積システム1993 · 1993年8月 ～
• ロボットエレクトロニクスシステム1993 · 1993年8月 ～
• 瞬時応答性を有する知能集積システム用VLSIプロセッサのハイレベルシンセシス亀山 充隆, 張山 昌論, 羽生 貴弘
• 量子アニーリングアシスト材料計算科学のためのカスタムアクセラレータ基盤張山 昌論, Waidyasooriya Ha

• Official profile