Tokyo University of Agriculture and Technology · Graduate School of Engineering / Institute of Engineering · 助教

Research keywordscompression router for low-latency・selective data compression・distance aware compression・low-latency high-bandwidth interconnection・latency high bandwidth interconnection・performance of interconnection・packet compression

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• A Compression Router for Low-Latency Network-on-Chip
• The Case for Coherence Directories in Memory Cubes
• An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization
• The Case for Water-Immersion Computer Boards

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