Tokyo Metropolitan University · Graduate School of System Design / Faculty of System Design · 教授

Research keywordsbinary neural networks・recognition accuracy・FPGA testing・process variation measurement・MOSFET aging・delay measurement・soft error tolerance・hardware reliability

Research fieldsInformatics・情報科学・社会システム工学・Integrated Science and Innovative Science・Integrated Disciplines・Comprehensive Fields・Complex systems・Computing Technologies

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• Analyzing the Impact of Weight Faults on Recognition Accuracy in Binary Neural Networks, FIT(2025)2025 · 研究業績 · _other
• A Method for Measuring Process Variations in the FPGA Chip Considering the Effect of Wire Delay, IOLTS'21 (2021).2021 · 研究業績 · _other
• On-Chip Delay Measurement for In-Field Test, VTS'20 (2020).2020 · 研究業績 · _other
• On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test, IOLTS'20 (2020).2020 · 研究業績 · _other

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